/*
** ############################################################################
**     Project   : osdee - Operative Systems Design for Embedded Envrionments
**     File      : Isr.h
**     Revision  ; 1.0
**     Abstract  :
**         Predefined Interruption Service Routines implementation.
**     Processor : MC9S12XEP100CVL
**     Version   : Component 01.042, Driver 01.05, CPU db: 3.00.036
**     Datasheet : MC9S12XEP100 Rev. 1.19 12/2008
**
**     Copyright : 2014 Fernando Rodriguez, Open source with out any responsability.
**     
**     mail      : frr@gmail.com
** ############################################################################
*/

#include "isr.h"
#include "MCU.h"

/* Startup defined in Start12.c */
extern void interrupt _Startup( void  );

/*lint -save  -e765 Disable MISRA rule (8.10) checking. */
#pragma CODE_SEG __NEAR_SEG NON_BANKED
/*
** ===================================================================
**     Method      :  Mcu_vIsr_default(void)
**
**     Description :
**         Default isr function to be called 
**         when a non configured Interrupt is triggered.
** ===================================================================
*/
__interrupt void Mcu_vIsr_default(void)
{
}
#pragma CODE_SEG DEFAULT


/*lint -restore Enable MISRA rule (8.10) checking. */

/*lint -save  -e950 Disable MISRA rule (1.1) checking. */
/* Initialization of the CPU registers in FLASH */
/*lint -restore Enable MISRA rule (1.1) checking. */

/* Interrupt vector table */

#ifndef UNASSIGNED_ISR
  #define UNASSIGNED_ISR Mcu_vIsr_default   /* unassigned interrupt service routine */
#endif

/*lint -save  -e950 Disable MISRA rule (1.1) checking. */
void (* near const _InterruptVectorTable[])(void) @ 0xFF10U =
{
/*lint -restore Enable MISRA rule (1.1) checking. */
  &UNASSIGNED_ISR,                       /* 0x08  0xFF10   -   -    ivVsi           unused by PE */
  &UNASSIGNED_ISR,                       /* 0x09  0xFF12   -   -    ivVsyscall      unused by PE */
  &UNASSIGNED_ISR,                       /* 0x0A  0xFF14   -   -    ivVmpuaccesserr unused by PE */
  &UNASSIGNED_ISR,                       /* 0x0B  0xFF16   -   no   ivVxsei         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x0C  0xFF18   1   no   ivVReserved115  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x0D  0xFF1A   1   no   ivVReserved114  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x0E  0xFF1C   1   no   ivVReserved113  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x0F  0xFF1E   1   no   ivVReserved112  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x10  0xFF20   1   no   ivVReserved111  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x11  0xFF22   1   no   ivVReserved110  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x12  0xFF24   1   no   ivVReserved109  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x13  0xFF26   1   no   ivVReserved108  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x14  0xFF28   1   no   ivVReserved107  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x15  0xFF2A   1   no   ivVReserved106  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x16  0xFF2C   1   no   ivVReserved105  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x17  0xFF2E   1   no   ivVReserved104  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x18  0xFF30   1   no   ivVReserved103  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x19  0xFF32   1   no   ivVReserved102  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x1A  0xFF34   1   no   ivVReserved101  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x1B  0xFF36   1   no   ivVReserved100  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x1C  0xFF38   1   no   ivVReserved99   unused by PE */
  &UNASSIGNED_ISR,                       /* 0x1D  0xFF3A   1   no   ivVReserved98   unused by PE */
  &UNASSIGNED_ISR,                       /* 0x1E  0xFF3C   1   no   ivVatd1compare  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x1F  0xFF3E   1   no   ivVatd0compare  unused by PE */
  &UNASSIGNED_ISR,                       /* 0x20  0xFF40   1   no   ivVtimpaie      unused by PE */
  &UNASSIGNED_ISR,                       /* 0x21  0xFF42   1   no   ivVtimpaaovf    unused by PE */
  &UNASSIGNED_ISR,                       /* 0x22  0xFF44   1   no   ivVtimovf       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x23  0xFF46   1   no   ivVtimch7       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x24  0xFF48   1   no   ivVtimch6       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x25  0xFF4A   1   no   ivVtimch5       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x26  0xFF4C   1   no   ivVtimch4       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x27  0xFF4E   1   no   ivVtimch3       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x28  0xFF50   1   no   ivVtimch2       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x29  0xFF52   1   no   ivVtimch1       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x2A  0xFF54   1   no   ivVtimch0       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x2B  0xFF56   1   no   ivVsci7         unused by PE */
  Mcu_vPIT_Channel7_Isr,                 /* 0x3D  0xFF7A   1   no   ivVpit7                      */
  Mcu_vPIT_Channel6_Isr,                 /* 0x3D  0xFF7A   1   no   ivVpit6                      */
  Mcu_vPIT_Channel5_Isr,                 /* 0x3D  0xFF7A   1   no   ivVpit5                      */
  Mcu_vPIT_Channel4_Isr,                 /* 0x3D  0xFF7A   1   no   ivVpit4                      */
  &UNASSIGNED_ISR,                       /* 0x30  0xFF60   1   no   ivVReserved79   unused by PE */
  &UNASSIGNED_ISR,                       /* 0x31  0xFF62   1   no   ivVReserved78   unused by PE */
  &UNASSIGNED_ISR,                       /* 0x32  0xFF64   1   no   ivVxst7         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x33  0xFF66   1   no   ivVxst6         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x34  0xFF68   1   no   ivVxst5         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x35  0xFF6A   1   no   ivVxst4         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x36  0xFF6C   1   no   ivVxst3         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x37  0xFF6E   1   no   ivVxst2         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x38  0xFF70   1   no   ivVxst1         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x39  0xFF72   1   no   ivVxst0         unused by PE */
  Mcu_vPIT_Channel3_Isr,                 /* 0x3D  0xFF7A   1   no   ivVpit3                      */
  Mcu_vPIT_Channel2_Isr,                 /* 0x3D  0xFF7A   1   no   ivVpit2                      */
  Mcu_vPIT_Channel1_Isr,                 /* 0x3D  0xFF7A   1   no   ivVpit1                      */
  OS_Entry_Mcu_vPIT_Channel0_Isr,                 /* 0x3D  0xFF7A   1   no   ivVpit0                      */
  &UNASSIGNED_ISR,                       /* 0x3E  0xFF7C   1   -    ivVhti          unused by PE */
  &UNASSIGNED_ISR,                       /* 0x3F  0xFF7E   1   no   ivVapi          unused by PE */
  &UNASSIGNED_ISR,                       /* 0x40  0xFF80   1   no   ivVlvi          unused by PE */
  &UNASSIGNED_ISR,                       /* 0x41  0xFF82   1   no   ivViic1         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x42  0xFF84   1   no   ivVsci5         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x43  0xFF86   1   no   ivVsci4         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x44  0xFF88   1   no   ivVsci3         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x45  0xFF8A   1   no   ivVsci2         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x46  0xFF8C   1   no   ivVpwmesdn      unused by PE */
  &UNASSIGNED_ISR,                       /* 0x47  0xFF8E   1   no   ivVportp        unused by PE */
  &UNASSIGNED_ISR,                       /* 0x48  0xFF90   1   no   ivVcan4tx       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x49  0xFF92   1   no   ivVcan4rx       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x4A  0xFF94   1   no   ivVcan4err      unused by PE */
  &UNASSIGNED_ISR,                       /* 0x4B  0xFF96   1   no   ivVcan4wkup     unused by PE */
  &UNASSIGNED_ISR,                       /* 0x4C  0xFF98   1   no   ivVcan3tx       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x4D  0xFF9A   1   no   ivVcan3rx       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x4E  0xFF9C   1   no   ivVcan3err      unused by PE */
  &UNASSIGNED_ISR,                       /* 0x4F  0xFF9E   1   no   ivVcan3wkup     unused by PE */
  &UNASSIGNED_ISR,                       /* 0x50  0xFFA0   1   no   ivVcan2tx       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x51  0xFFA2   1   no   ivVcan2rx       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x52  0xFFA4   1   no   ivVcan2err      unused by PE */
  &UNASSIGNED_ISR,                       /* 0x53  0xFFA6   1   no   ivVcan2wkup     unused by PE */
  &UNASSIGNED_ISR,                       /* 0x54  0xFFA8   1   no   ivVcan1tx       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x55  0xFFAA   1   no   ivVcan1rx       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x56  0xFFAC   1   no   ivVcan1err      unused by PE */
  &UNASSIGNED_ISR,                       /* 0x57  0xFFAE   1   no   ivVcan1wkup     unused by PE */
  &UNASSIGNED_ISR,                       /* 0x58  0xFFB0   1   no   ivVcan0tx       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x59  0xFFB2   1   no   ivVcan0rx       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x5A  0xFFB4   1   no   ivVcan0err      unused by PE */
  &UNASSIGNED_ISR,                       /* 0x5B  0xFFB6   1   no   ivVcan0wkup     unused by PE */
  &UNASSIGNED_ISR,                       /* 0x5C  0xFFB8   1   no   ivVflash        unused by PE */
  &UNASSIGNED_ISR,                       /* 0x5D  0xFFBA   1   no   ivVflashfd      unused by PE */
  &UNASSIGNED_ISR,                       /* 0x5E  0xFFBC   1   no   ivVspi2         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x5F  0xFFBE   1   no   ivVspi1         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x60  0xFFC0   1   no   ivViic0         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x61  0xFFC2   1   no   ivVsci6         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x62  0xFFC4   1   no   ivVcrgscm       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x63  0xFFC6   1   no   ivVcrgplllck    unused by PE */
  &UNASSIGNED_ISR,                       /* 0x64  0xFFC8   1   no   ivVectpabovf    unused by PE */
  &UNASSIGNED_ISR,                       /* 0x65  0xFFCA   1   no   ivVectmdcu      unused by PE */
  &UNASSIGNED_ISR,                       /* 0x66  0xFFCC   1   no   ivVporth        unused by PE */
  &UNASSIGNED_ISR,                       /* 0x67  0xFFCE   1   no   ivVportj        unused by PE */
  &UNASSIGNED_ISR,                       /* 0x68  0xFFD0   1   no   ivVatd1         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x69  0xFFD2   1   no   ivVatd0         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x6A  0xFFD4   1   no   ivVsci1         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x6B  0xFFD6   1   no   ivVsci0         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x6C  0xFFD8   1   no   ivVspi0         unused by PE */
  &UNASSIGNED_ISR,                       /* 0x6D  0xFFDA   1   no   ivVectpaie      unused by PE */
  &UNASSIGNED_ISR,                       /* 0x6E  0xFFDC   1   no   ivVectpaaovf    unused by PE */
  &UNASSIGNED_ISR,                       /* 0x6F  0xFFDE   1   no   ivVectovf       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x70  0xFFE0   1   no   ivVectch7       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x71  0xFFE2   1   no   ivVectch6       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x72  0xFFE4   1   no   ivVectch5       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x73  0xFFE6   1   no   ivVectch4       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x74  0xFFE8   1   no   ivVectch3       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x75  0xFFEA   1   no   ivVectch2       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x76  0xFFEC   1   no   ivVectch1       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x77  0xFFEE   1   no   ivVectch0       unused by PE */
  &UNASSIGNED_ISR,                       /* 0x78  0xFFF0   1   no   ivVrti          unused by PE */
  &UNASSIGNED_ISR,                       /* 0x79  0xFFF2   1   no   ivVirq          unused by PE */
  &UNASSIGNED_ISR,                       /* 0x7A  0xFFF4   -   -    ivVxirq         unused by PE */
  Mcu_vSWI_Isr,                         /* 0x7B  0xFFF6   -   -    ivVswi          unused by PE */
  &UNASSIGNED_ISR,                       /* 0x7C  0xFFF8   -   -    ivVtrap         unused by PE */
  _Startup,                              /* 0x7D  0xFFFA   -   -    ivVcop                       */
  Mcu_vPll_Clock_Monitor_Isr,            /* 0x7E  0xFFFC   -   -    ivVclkmon                    */
  _Startup                               /* 0x7F  0xFFFE   -   -    ivVreset                     */
};
